| 摘要 |
An arithmetic logic unit has elementary cells performing logical addition, one for each pair of operand bits, which are optimized for carry propagation speed and are controlled by auxiliary logic allowing them to perform additional operations; the unit further comprises a control signal generating circuit, subdivided into a first part, adjacent the elementary cell handling the least significant operand bits, which generates an operation selection signal for all the cells, and a second part, adjacent the elementary cell handling the most significant operand bits which generates control signals for the auxiliary logic of each elementary cell. |
