发明名称 |
Low-power parallel multiplier |
摘要 |
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.
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申请公布号 |
US4982355(A) |
申请公布日期 |
1991.01.01 |
申请号 |
US19890300492 |
申请日期 |
1989.01.20 |
申请人 |
OKI ELECTRIC INDUSTRY COMPANY INC. |
发明人 |
NISHIMURA, EIICHI;NAKAMURA, TAKAO;ISHIDA, HISAKI |
分类号 |
G06F7/53;G06F7/508;G06F7/52;G06F7/76 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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