发明名称 Plural processor inferencing system and method
摘要 An inference processing system comprises a plurality of processors assigned for nodes of a semantic network respectively to carry out parallel processing. Each of the processors stores tables and linking information. The tables are made by arranging rules and prepared for goals respectively. Each table contains the names of links to follow when a certain goal is given and markers for specifying the kinds of the links. In the table, the link names and markers are set as outputs with respect to the given goal as an input. The linking information contains information of links connected to a node for which a corresponding one of the processors is assigned. When the goal and a marker are inputted to any one of the processors, the processor finds an output marker and output links in the tables and linking information and outputs the output marker to the output links, thus achieving an inference process.
申请公布号 US4982340(A) 申请公布日期 1991.01.01
申请号 US19880212490 申请日期 1988.06.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 OYANAGI, SHIGERU;FUJITA, SUMIKAZU;NAKAMURA, SADAO;SUZUOKA, TAKASHI
分类号 G06F9/44;G06N5/04 主分类号 G06F9/44
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