Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers

摘要

The present invention utilizes a wet or vapor isotropic etchback process of carefully controlled duration to create a field-effect transistor having reduced-slope, staircase-profile sidewall spacers formed from a pair of TEOS oxide layers. The spacer's reduced sidewall slope and staircase profile facilitates digit line deposition and aids in reducing the existence of short-prone polysilicon stringers.