发明名称 Communication apparatus for reassembling packets received from a network into a message.
摘要 <p>In a network having a plurality of node apparatuses (200A-200F) connected to a transmission line (100), each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting time to the transmission line (100) in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory . There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory blocks.</p>
申请公布号 EP0404078(A2) 申请公布日期 1990.12.27
申请号 EP19900111593 申请日期 1990.06.19
申请人 HITACHI, LTD.;HITACHI MICROCOMPUTER ENGINEERING LTD. 发明人 TAKIYASU, YOSHIHIRO;YAMAGA, MITSUHIRO;NAKAMURA, KAZUNORI;AMADA, EIICHI;JUSA, HIDEHIKO;KOBAYASHI, NAOYA;TAKADA, OSAMU;HIRAYAMA, SATORU;IIYAMA, TATSUHITO
分类号 H04L13/08;H04L12/813;H04L12/815;H04L12/863;H04L12/951 主分类号 H04L13/08
代理机构 代理人
主权项
地址