发明名称 TROUBLE REPORTING SYSTEM FOR MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To eliminate a trouble display device, a cable driver, etc., by using a common bus and an interface circuit to read trouble indications of a slave processor from a master processor. CONSTITUTION:Fixed master processor 1 and slave processors 3 and 4 are connected through a common bus 2, and slave processors 3 and 4 consist of interface circuits 5 and 6, CPUs 7 and 8, and trouble indication registers 9 and 10. The trouble information read command received from the master processor 1 through the common bus 2 is decoded by interface circuits 5 and 6, and much urgent information in trouble indication registers 9 and 10 and information of the change request of the system are edited and are returned to the master processor 1 through the common bus 2. Thus, a trouble display device, a cable driver, and a relay are eliminated.
申请公布号 JPS57191757(A) 申请公布日期 1982.11.25
申请号 JP19810076968 申请日期 1981.05.21
申请人 NIPPON DENKI KK 发明人 ISOGAWA YOUICHI
分类号 G06F11/16;G06F15/16;G06F15/177 主分类号 G06F11/16
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