| 摘要 |
<p>PURPOSE:To shorten a memory access time by orderly reading a group of data from a memory cell array in accordance with access addresses which is synchronized with external control signals from latched addresses as starting points and renewed. CONSTITUTION:The device is provided with address signal forming means 3 and 5 which latch arbitrary address signals A0-An supplied from an external and orderly output address signals which are updated synchronizing with the external control signals from the latched addresses as the starting points and orderly renewed. According to the output of the address signal forming means 3 and 5, addressing a memory cell 2 is performed. Thus when a group of data is continuously read or variable-length data is read for each group, such external burdens as address operation are reduced and the memory access time for reading the group of data can be shortened.</p> |
