| 摘要 |
An integrated circuit apparatus for performing digital synthesis of regular waveforms having transitions at arbitrary points in time is disclosed. A reference clock signal is provided as input to a synchronous delay line apparatus, producing a plurality of taps. The taps signal provides N inputs to a digital-to-time domain converter (DTC), where N is the resolution of the synthesized waveform, said DTC apparatus further receiving inputs from a pattern generator apparatus over a shifter apparatus and a pattern register apparatus. The DTC apparatus combines the taps signal and the input from said pattern register to produce a synthesized waveform. In the presently preferred embodiment, the DTC apparatus comprises a plurality of pairs of N-type and P-type devices connected as transmission gates. When the transmission gate is turned on, it transfers the input pattern bits to the output line. When the transmission gate is turned off, it effectively has an infinite impedance and isolates the input pattern from the output line. Only one transmission gate in the DTC apparatus is turned on at one time. The waveform pattern register apparatus has varying depths of master and slave latches. It receives pattern inputs from the pattern generator apparatus and outputs in three separate fields to the DTC apparatus. The bits of the first field of the pattern waveform register are implemented as a solitary master stage. The bits of the second field of the waveform pattern register are implemented as complete master-slave pairs. The bits of the third field of the waveform pattern register are implemented as master-slave-master triads.
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