发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To stably obtain a signal accurately synchronized with a synchronizing signal by inhibiting the output of a synchronizing signal separating circuit from being supplied to a PLL circuit for a period wherein at least either of an equivalent pulse and a signal for damping prevention is generated. CONSTITUTION:A synchronizing signal separating circuit 11 compares an input video signal with a specific reference level and separates, detects, and supplies the equivalent pulse and signal for damping prevention to a vertical synchronizing signal separating circuit 12 to detect the vertical synchronizing signal in addition to a horizontal synchronizing signal and the vertical synchronizing signal, thereby outputting a signal with logic H while the vertical synchronizing signal is detected. A switch 18 is turned off when a pulse generating circuit 19 outputs the logic H and turned on when logic L is outputted. Consequently, the output of a monostable multivibrator 1 is inputted to a sample holding circuit 2 only for a period wherein the pulse generating circuit 19 outputs the logic L and not transmitted while the logic H is outputted.</p>
申请公布号 JPH02309778(A) 申请公布日期 1990.12.25
申请号 JP19890131052 申请日期 1989.05.24
申请人 VICTOR CO OF JAPAN LTD 发明人 SHIBAYAMA TAKECHIKA;OZAKI HIDETOSHI
分类号 H04N5/06;H04N5/913;H04N5/932;H04N19/00;H04N19/70;H04N19/80 主分类号 H04N5/06
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