| 摘要 |
PURPOSE:To avoid the rapid increase in the current of a MOS transistor or a substrate current as well as the deterioration in the reliability on the chip operation by a method wherein the impurity concentration of a semiconductor substrate or a well is specified to cover a specific range. CONSTITUTION:A substrate 1 or a well 2 forming an enhancement type MOS transistor thereon is formed so that the impurity concentration therein may almost reach 1X10<15>cm<-3>-3X10<16>cm<-3> to lessen the back gate bias effect of the MOS transistor. Accordingly, even if the potential Vsub of the substrate 1 or the well 2 reaches the built-in potential when the power supply voltage exceeds the specific value or the current of the substrate 1 or the well 2 exceeds the pick up current of a substrate bias generating circuit 11 in case of throwing a power supply, the depression of the MOS transistor can be avoided. Through these procedures, the rapid increase in the current of the MOS transistor or the substrate current can be avoided thereby obviating the defect having a hysteresis to deteriorate the reliability on the chip operation. |
