Single polysilicon layer transistor with reduced emitter and base resistance

摘要

A single layer polysilicon self-aligned transistor (52) is provided having a substantially vertical emitter contact region (62), such that the emitter contact region (62) does not require extending portions overlying the base region (60). Heavily doped silicided regions (68) are disposed adjacent the emitter (64) in a self-aligned process such that the base resistance of the device is minimized. A planar oxide layer (72) is formed such that the emitter contact region (62) are exposed without exposing other polysilicon gates of the integrated circuit. A metal layer (76) may be disposed over the planar oxide layer (72) to form a level of interconnects.