| 摘要 |
PURPOSE:To perform a counter test in a short time and to decrease a signal line for a test clock, by adding the test clock directly to a test circuit gate without passing through a chattering preventing circuit. CONSTITUTION:A test input signal 451 is 1 in the state of test prohibition and an output 456 of a delay type flip-flop 430 is set at 1. Accordingly, AND gate 436 is not formed and although an accelerating clock for test is putted from a switch C terminal 401, a clock signal for test 462 is not generated. While, a correcting signal from the C terminal is inputted 443 to a chattering preventing circuit and is outputted from an output line 462. When a test operation is carried out, a switch data output 449 from a switch C series of the chattering preventing circuit becomes 0 and the function of the chattering preventing circuit is locked and a signal 442 for test added from the terminal 401 is outputted from the line 462. |
