| 摘要 |
<p>PURPOSE:To improve reliability by performing readout alternately with erasure and write repeatedly in an erase cycle and a write cycle with a clock signal, and completing an operation when data is set at an erase level or a write level. CONSTITUTION:The clock signal CLK is operated with the start of a rewrite cycle, and the erasure and the readout are performed alternately in the erase cycle, and the write and the readout are performed alternately in the write cycle with a control circuit 2. A system is comprised so that all bits in a byte performing rewrite can be set at '1's in the erase cycle, and when read out data changes to '1', a rewrite completion detection circuit 3 generates an erasure completion signal, then, the erase cycle is completed. In the next write cycle, the write is repeated, and when readout data changes from '1' to '0', all rewrite cycles are completed. Thereby, the reliability for the completion of the erasure and the write can be improved.</p> |
