发明名称 BIT BUFFER CIRCUIT FOR DATA COMMUNICATION EQUIPMENT
摘要 <p>PURPOSE:To surely prevent the consecutive error occurrence of a reception data by applying inversion every time the rising timing of an internal clock and that of a transmission clock of an external device approach together. CONSTITUTION:The transmission data of an external equipment 2 is latched with a clock supplied from the equipment 2 by a latch circuit 10. Moreover, the output of the circuit 10 is latched by a latch circuit 12 with a clock obtained in the inside of a data communication equipment 4. Furthermore, the output of the circuit 12 is latched by a latch circuit 14 by using the clock acquired in the inside of the equipment 4. Then the rising timing of the clock supplied form the external equipment 2 and that of the clock obtained in the inside of the equipment 4 are detected by a detection circuit 16 and the internal clock of the equipment 4 is inverted by an inverting circuit 18 every time both the detection timings are approached.</p>
申请公布号 JPH02308634(A) 申请公布日期 1990.12.21
申请号 JP19890129519 申请日期 1989.05.23
申请人 FUJITSU LTD 发明人 MATSUDA TAKAO
分类号 G06F5/06;H04L7/00 主分类号 G06F5/06
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