| 摘要 |
The circuit, which includes a bistable flip-flop 1, control circuit 2, 3, an output buffer 5 and a section 10 for producing precharging pulses, as well as a precharging section 9, includes a section 15 for producing data transition signals comprising MOS transistors M7, M8, bistable flip-flops 11, 12 connected to the MOS transistor, inverters and NAND gates ND1, ND2 serving to receive control precharging pulses, and the precharging section 9 consists of MOS transistors M5, M6, whose gates receive the output signals from the said section 15. Application in particular to enhanced semiconductor DRAM memory devices. <IMAGE>
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