| 摘要 |
PURPOSE:To obtain a small-sized speech clock of low consumption of power by jointly using the same oscillator for a clock for operating LSI for the clock and LSI for synthesizing a speech. CONSTITUTION:A stage counter of three bits of the like is provided in a speech data delivery controlling circuit 6 on which clocks of 2KHz or the like are impressed from a generator 12 of a clock generating circuit 11 of LSIVPC for synthesizing a speech based on an output of a quartz oscillator X' employed for LSI for clock. By employment of this stage counter, each processing stage is divided into eight and all synthesizing processings required within eight sampling times wherein delta modulation data of one byte are delivered serially through the intermediary of a conversion cable 1, a data delivering circuit 3, ROM2, etc. are performed. Accordingly, the increment velocity of the stage counter of three bits can be made to be the same with the sampling velocity of a delivered speech, the processing at the same velocity with that of sampling can be performed by jointly using the oscillator X' having low frequency, and thus a small- sized speech clock of low consumption of power is obtained. |
