发明名称 Method for treating copper circuit pattern of interlayer circuit board.
摘要 <p>A method for processing copper circuit pattern of interlayer circuit board carries out a reduction treatment with respect to the copper circuit pattern by causing a reducing gas to act on a surface of an oxide of copper formed on the copper circuit pattern for its surface roughening. A strong reducing action is thereby provided to the roughened surface of the oxide of copper and, consequently, the interlayer circuit board having the copper circuit pattern in which the oxide of copper mainly comprising cupric oxide is varied to cuprous oxide or a metallic copper can be obtained.</p>
申请公布号 EP0402966(A2) 申请公布日期 1990.12.19
申请号 EP19900201118 申请日期 1990.05.03
申请人 MATSUSHITA ELECTRIC WORKS, LTD. 发明人 AWANO, TOMIO, C/O MATSUSHITA ELECTRIC WORKS, LTD.;AKAMATSU, MOTOYUKI, C/O MATSUSHITA ELECTRIC WORKS;YAMANE, TOMOAKI, C/O MATSUSHITA ELECTRIC WORKS;ICHIKI, TSUTOMU, C/O MATSUSHITA ELECTRIC WORKS;FUNO, HIDEO, C/O MATSUSHITA ELECTRIC WORKS;SAGARA, TAKASHI, C/O MATSUSHITA ELECTRIC WORKS
分类号 H05K3/46;H05K3/38 主分类号 H05K3/46
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