| 摘要 |
PURPOSE: To enable the execution of both transient and intrinsic fault inspections at a time by sequentially and repeatedly strobing the second clock signal followed by the first clock signal during a plurality of timing cycles until all the logic data are read. CONSTITUTION: A complete inspection bit pattern is not achieved by the L2 latch at the end of C2 cycle, but is utilized at the input gate to the L2 latch. B clock is pulsed at a cycle C4 to latch a complete inspection bit pattern to the L2 latch of the SRL pair 12 and 14, and the inspection bit begins to be propagated in a logic circuit under inspection. In the latter half of the cycle C4, since the A/C clock is pulsed, and the SG signal is in the parallel mode during the cycle C4, the L1 latch of the output SRL uses inputs D10 and D11 to acquire available data from the logic circuit. Thus, this, both the intrinsic and transient fault inspections can be executed. |
