发明名称 INFORMATION PROCESSING SYSTEM
摘要 PURPOSE:To require the mounting of only a shared ROM by successively reading out control programs from the shared ROM and simultaneously or successively writing them in RAMs of CPU modules including a seef CPU module to load down control programs. CONSTITUTION:A CPU 113 enables the driver receiver circuit (DRV RCV) 114 of a master CPU module and receiver circuits (RCV) 124, etc., of respective CPU modules by a receiver enable signal 500 and is logically connected to respective local busses (LBUS) 115, 125... etc., and a system bus (SBUS) 300 and successively reads control programs stored in a shared ROM 200 and simultaneously or successively writes them in RAMs 112, 122... of CPU modules. Thereafter, the CPU 113 of the master CPU module invalidates the DRV RCV 114 and RCVs 124... by the receiver enable signal 500 and logically disconnects LBUSs 115, 125... and the SBUS 300 and starts CPUs 123... of respective CPU modules to execute stored control modules. Thus, mounting of only the shared ROM 200 is required.
申请公布号 JPH02300843(A) 申请公布日期 1990.12.13
申请号 JP19890120324 申请日期 1989.05.16
申请人 NEC ENG LTD 发明人 KYOTANI YUICHI
分类号 G06F15/177;G06F9/445;G06F13/00;G06F15/16 主分类号 G06F15/177
代理机构 代理人
主权项
地址