| 摘要 |
PURPOSE: To make it possible to selectively execute plural arithmetic operations in parallel by providing a central processor with a set of dedicated arithmetic instructions for executing a narrow gauge instruction. CONSTITUTION: A CPU 10 consists of 4 independent processors 12a to 12d sharing the access to an instruction cache 14, a data cache 16, a memory control unit 18, and a memory/bus interface 20. Further, each of 'parallel addition', 'partial subtraction' and 'partial comparison' instructions executes arithmetic operation for bytes or half words where two operands are corresponding to each other, and returns the result in unit of byte or half word to the processor. The partial multiplication instruction multiplies a multiplicand in unit of byte or half word by a common multiplier, and returns the product in unit of byte or half word to the processor, and the carry condition codes are individually maintained for each half word or each byte. The partial carry load instruction code extends the carry condition codes to each half word or byte. Thereby, multigauge arithmetic operations can be executed at high speed. |
