Semiconductor memory cell having high density structure.

摘要

In a semiconductor memory cell of a DRAM comprising a stacked cell capacitor (310a,310b) constructed upon word and bit lines (304a,304b,304c,314a,314b) the stacked cell capacitor is not directly connected to a transistor. A local wiring from the diffusion layer of the transistor to the device isolator area is provided. Through this wiring, the diffusion layer of the transistor is connected to the stacked cell capacitor (310a,310b). Also, a bit line is contructed on the active region to cross the connection point between the transistor, local wiring and gate electrode.