发明名称 |
Digital arrangement for error checking in binary adder including block carry look-ahead units. |
摘要 |
A binary adder is comprised of a plurality of block carry look-ahead units. Each of the units includes a block carry-in generator (38), an adding section (40), a block carry-out generator (102) and a carry coincidence checker (110). The block carry-in generator (38) is arranged to receive a plurality of carry generate variables and a plurality of carry propagate variables from the other units, generating a carry-in using carry look-ahead scheme. The adding section (40) is coupled to receive the carry-in from said block carry-in generator (38) and further receives two operand data to be added and generates a resultant sum of the two operand data. The block carry-out generator (102) receives the two operand data and also receives the carry-in from the block carry-in generator (38). The block carry-out generator (102) produces a carry-out of the unit to be applied to a lower order block carry look-ahead unit. The carry coincidence checker (110) is arranged to receive the carry-in from the carry-in generator (38) and also receives a carry from another block carry look-ahead unit. The carry, which is applied from another unit, corresponds to the carry-out. The checker (110) performs a coincidence check between the carry-in and the carry applied from another unit.
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申请公布号 |
EP0401783(A2) |
申请公布日期 |
1990.12.12 |
申请号 |
EP19900110694 |
申请日期 |
1990.06.06 |
申请人 |
NEC CORPORATION |
发明人 |
TANAKA, MASAYUKI, C/O NEC CORPORATION |
分类号 |
G06F7/499;G06F7/50;G06F7/506;G06F7/508;G06F11/10;G06F11/16;G06F11/267 |
主分类号 |
G06F7/499 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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