发明名称 METHOD FOR FORMING AUTOMATIC TEST CIRCUIT OF INTEGRATED CIRCUIT
摘要 PURPOSE:To facilitate the test planning of an LSI containing a memory by storing the rule related to the test of the memory and logical items in a memory means for a logic trouble judging rule and logical items and forming a memory testing circuit by a memory testing circuit forming means. CONSTITUTION:A rule memory means 1 and a logical item memory means 2 storing a rule and logical items are used for the sake of the trouble judgement to the logic part of an LSI and a scanning test circuit is automatically formed by a scanning circuit forming means 3. In this case, the LSI contains a memory part and, when the LSI is tested, the rule and logical items to the memory part are stored in the means 1, 2. Subsequently, the data of the means 1, 2 are used and a memory testing circuit is formed by a separately provided memory testing circuit forming means 4 to store said data in a memory testing data memory means 5. Next, the data of the means 5 are taken out to be applied to the external terminal of a chip to test the memory part.
申请公布号 JPH02298877(A) 申请公布日期 1990.12.11
申请号 JP19890060200 申请日期 1989.03.13
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 AIKYO TAKASHI;KARASAWA NAOKO;SUEHIRO YOSHIYUKI;TAKAOKA HARUYOSHI
分类号 G01R31/28;G06F11/22;G06F17/50;G11C29/00;G11C29/12 主分类号 G01R31/28
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