| 摘要 |
<p>PURPOSE:To reduce the chip area and to improve the reliability by providing memory cells for flags in part of a memory cell array and using sense amplifiers and a write circuit even for normal data writing and reading operation in common. CONSTITUTION:When data are written in respective memory cells 1 and flag memory cells 9 of the programmable memory cell array 3, a two-directional decoder circuit 6-1 drives one word line 5 or 10 and selects the cells 1 or 9. At this time, electrons are implanted to floating gates of the selected memory cells 1 or 9 to write the data. The data stored in the cells 9 are read out through sense amplifiers 7 common to the cells 1. Consequently, the occupation area of a flag circuit is reduced and the area of a chip pattern is also reduced; and variance in the characteristics is small and the reliability is improved.</p> |
