| 摘要 |
PURPOSE:To easily generate a stable delay signal by providing a 1st inverter array circuit comprising the connection of odd number of stages of inverters and a 2nd inverter array circuit comprising the inverters of the same constitution as the 1st inverter array circuit and constituting a ring counter and forming the 1st and 2nd inverter array circuits on one and same chip. CONSTITUTION:A 2nd inverter array circuit 37 consists of inverters 37a-37n connected in series in odd number stages, an output of the inverter 37n of the final stage connects to the input side of the inverter 37a of the 1st stage and the inverters are connected as a loop and the circuit 37 applies self excitation oscillation at the natural frequency. The frequency is a reciprocal of the sum of delay time per one stage of the 2nd inverter array circuit 37. The phase of the output and a reference clock 2 having a prescribed frequency at a frequency divider 32 generated in the oscillator 31 are compared by a phase comparator 35 and its difference is converted into a voltage by a low pass filter 34 and the voltage is fed to the 2nd inverter array circuit 37. In this case, when the control voltage gets higher, the oscillating frequency is increased and a stable ring counter oscillating frequency is obtained. |
