发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent the frequency of an output clock from varying by connecting two diodes to the feedback path between the input and output of an amplifying circuit in parallel so that the polarities are opposite. CONSTITUTION:The output signal of a phase comparing circuit(PC) 3 which inputs an external clock inputted from a terminal 1 and an output clock from a terminal 2 is supplied to the input terminal of an inverting amplifier 4, a resistance 7, the anode of a diode 8, and the cathode of a diode 9. Further, the output signal of the inverting amplifier 4 is inputted to a voltage-controlled oscillation circuit (VCO) 5 and supplied to the resistance 7, the cathode of the diode 8, and the anode of the diode 9, and the output signal of the voltage- controlled oscillation circuit 5 is outputted from the terminal 2. Thus, the diodes 8 and 9 are connected to the feedback path of the amplifying circuit in parallel in the opposite polarity state and the output amplitude of the amplifying circuit is suppressed to the voltage drop across the diodes to suppress the variation in the frequency of the output clock of the voltage-controlled oscillation circuit.
申请公布号 JPH02295315(A) 申请公布日期 1990.12.06
申请号 JP19890117723 申请日期 1989.05.10
申请人 NEC CORP 发明人 KUDO TOSHIYUKI
分类号 H03L7/093;H04L7/033 主分类号 H03L7/093
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