| 摘要 |
A SAM data accessing circuit and a method thereof in which, at the falling edge of a serial counting clock signal SC occurring at one and half cycles before data output cycles, the data is sensed from a SAM port memory. The sensed data is then stored in a first section of a two-stage buffer. At the falling edge of the serial counting clock signal SC occurring at half-cycles before data output cycles, the data stored in the first stage of the buffer is transferred to a second stage thereof. At the rising edge of the serial counting clock signal SC, the data stored in the second section of the buffer is outputted. This sensing/outputting sequence reduces peak currents consumed by the I/O circuits. |
