| 摘要 |
PURPOSE: To reduce the size of a memory peripheral circuit by writing in and reading out a memory cell through a first and a second data lines, enhancing noise immunity against the change in technology and parameter modulation and eliminating the use 'of an analog circuit. CONSTITUTION: Write-in is carried out, in a six-transistor memory cell, through a write selective transistor N3' driven by a write word line WS from a write data line DS. Read-out on a read data line DL is carried out through a read selective transistor N4' driven by a word line WL. A cell signal is read out on the read data line DL through the read selective transistor N4' from an inverter I1' formed with N1' and P1'. No amplifier, which is expensive and easy to fail, is required in a memory cell for the purpose of recognizing a cell signal. The reason is that an inverter or a simple one level comparator circuit is sufficient for the evaluation of a cell signal. Thus, once again, noise immunity is enhanced against technological change, and also possibility is improved in the case of conversion to a dimensionally miniaturized geometry (contraction). |
