| 摘要 |
PURPOSE:To obtain a phase locked loop circuit capable of reducing the time till the synchronization is taken by matching the phase of a clock signal in response to a pulse signal received at first. CONSTITUTION:A receiver 1 converts a received pulse signal 10 into a binary signal 11 and outputs the result. A 1st pulse detection circuit 4 receives an edge signal 12 outputted from an edge detection circuit 2 and an INFO 0 detection signal 13 outputted from an INFO 0 (state of no signal) detection circuit 3 and outputs a 1st pulse signal 14 upon the detection of a first reception input signal. On the other hand, a PLL circuit 5 generates a timing clock 15 based on the edge signal 12 and the clock signal 16 from the counter circuit 6. When the counter circuit 6 receives the 1st pulse signal 14 at the start of transmission, the signal is loaded to a frequency divider counter to make the phase of the received pulse signal 10 close to the phase of the phase locked loop circuit. Thus, the time till the phase locking is taken is reduced. |
