| 摘要 |
<p>PURPOSE:To improve the execution speed to the maximum and to construct the system having reliability by varying the timing of a control signal of a memory to a CPU in accordance with a memory address. CONSTITUTION:The control of the timing of a control signal is optimized by using a delay by a buffer gate 204. That is, by a Read Write signal, the inverse of MEM 201 of a memory, signals of the timings, the inverse of RAS 202, the inverse of CAS 203 of the control signal are determined. These signals are optimized by setting the maximum and the minimum time of signal width in which a Parity Check occurs to each control signal, and adjusting the timing of the control signal in accordance with a temperature characteristic, etc., of the memory within the maximum - minimum time range by using selectors 205, 206, etc. In such a way, the execution speed is improved and the computer device having high reliability is obtained.</p> |
