| 摘要 |
1,127,047. Television. XEROX CORP. 2 Dec., 1965 [2 Dec., 1964], No. 51210/65. Headings H3T and H4F. A time and amplitude quantized two-level signal, in for example a fascimile system in which the two levels represent black and white, is generated from an amplitude quantized two-level signal and a series of clock signals defining clock intervals therebetween by comparing the time and amplitude quantized and amplitude quantized two-level signals during each clock interval, maintaining the time and amplitude quantized signal at one of the two levels during each clock interval, and changing the time and amplitude quantized signal to the other of the two levels at a clock signal if the time and amplitude quantized signal and amplitude quantized signal differed during the preceding clock interval. In a fascimile system this may be summarized as follows: if the " previous bit " (clock interval) was judged black, " this bit " i.e. the preceding clock interval which follows the " previous bit ", will be judged white at the clock signal immediately following " this bit ", if the video signal is white at any time during " this bit ", and vice versa. This decision-making rule may be modified so that if the " previous bit " was judged black, " this bit " will be judged white if the video signal is white for at least a predetermined percentage of " this bit ", and/or vice versa. These decision-making rules may be mixed so that the percentage required for a white-black transition is different from that required for a black-white transition. In Fig. 1 a video signal from scanner 10 is amplitude quantized into a two-level signal, zero and -12 v, in circuit 11 and applied to flip-flop circuit 14 via control diodes SR1 and SR4 and inverter Q1. If each of diodes SR1, SR2 and SR3 connected to input 13 of flip-flop 14 are returned to -12 v., then flip-flop 14 will switch to the state in which output 16 is zero and output 17 is -12 v. (black state). If one or more of these diodes is returned to zero, then none can have any effect on the operation of the flip-flop. Similar conditions arise at input 15. Timing and control circuit 12 which supplies the various conventional control signals also produces a clock signal, e.g. a square wave having voltage levels of zero and -12 v., which is applied via amplifiers Q2 and Q3 to produce a series of 1 micro-second negative-going pulses having the same repetition rate as the clock frequency. These pulses are inverted by transistor Q4 and applied to diodes SR3 and SR6 associated with inputs 13 and 15 of flipflop 14, and inverted again by transistor Q5 and applied to the inputs of the second flip-flop 22. Outputs 16, 17 of flip-flop 14 are connected to the inputs 23, 24 of flip-flop 22 as shown and a negative voltage on terminals 16 or 17 does not affect flip-flop 22 because of diodes SR7 and SR8. A zero voltage level on terminals 16 or 17 is not sufficiently positive to affect flipflop 22. However, the positive-going trailing edge of the clock pulse from Q5 and Q6 applied through capacitor C1 will cause flip-flop 22 to assume the black state wherein output 18 is at zero and output 19 is at -12 v., if output 16 is at zero volts and has been at zero volts long enough to charge capacitor C1 before the end of the clock pulse. Assume initially that flip-flop 22 is in the " white " state (output 18 at -12 v., and output 19 at zero) then since output 19 is connected to diode SR5 the video signal applied to diode SR4 has no effect on flip-flop 14. However diodes SR2 and SR3 are now returned to -12 v., and thus the first appearance of a -12 v. video signal at diode SR1 causes flip-flop 14 to switch to the " black " state. If flipflop 14 was previously in that state it will remain so. The arrival of a positive-going clock pulse at diodes SR3 and SR6 disables flip-flop 14. At the same time negative clock pulses are applied to capacitors C1 and C2 associated with flip-flop 22. If flip-flop 14 has switched to the " black " state (output 16 at zero), then flip-flop 22 is enabled to switch to the " black " state wherein output 19 is at -12 v. If this is so then diode SR2 will inhibit the effect of video signals applied to input 13 of flip-flop 14 through diode SR1. Whenever a video signal of -12 v. appears at diode SR4, flip-flop 14 will switch back to the " white " state (output 17 at zero) because of inverter Q1. The voltage at terminal 18, which is thus time quantized, has added to it synchronizing and control words during retrace intervals in OR gate 20. To reduce the sensitivity of the circuit of Fig. 1 to very small black or white areas a capacitor (C3, Fig. 2, not shown) is connected to terminal 13 which must first be charged up before the voltage on terminal 13 changes. Substitution of a Zener diode (SR11, Fig. 2, not shown) for the corresponding resistor of Fig. 1 is desirable in order to provide a constant and predictable time delay. |
