| 摘要 |
PURPOSE:To attain timing synchronization without use of a delay circuit and introduction of an external synchronization control signal by providing a timing detection circuit for an external input signal and a synchronization circuit for a detection output. CONSTITUTION:A level of a terminal Q of DFFs 6-8 goes sequentially to logical H individually corresponding to a timing of a level change of each signal of 3 input signals 104. The level of all terminals Q goes to logical H. An output of an AND gate 16, that is, a synchronizing control signal 105 goes to logical H in the timing of a signal varied latest among the input signals 104. When a synchronizing signal is inputted to a terminal C of DFFs 3-5 forming the synchronizing circuit 17, the signals 104 inputted to the terminal D are completely synchronized and all the DFFs 6-8 are reset by the synchronizing control signal inputted to a terminal R via a delay circuit 15 simultaneously to prepare the change in the succeeding input signal. Through the constitution above, no external synchronizing signal is required and a delay circuit for time adjustment is not entirely required. |
