发明名称 PEAK CURRENT HOLDING CIRCUIT
摘要 <p>PURPOSE:To keep a long holding time with a small time constant by providing both transistors for a 2nd bypass to allow a power source current to flow in accordance with decreasing tendency of a signal source current and for a 3rd bypass to allow the signal source current to flow interlocking the aforementioned one. CONSTITUTION:A transistor Tr Q1, Tr Q4 applied with the same base voltage as Tr Q1, and Tr Q5 made to be ON at the same time as Tr Q4 are connected, and the Tr Q5 is made so that a Tr Q6 forming a current mirror circuit with Trs Q7, 8 can be ON/OFF. When a current Iin is increased, a base potential of the Tr Q6 is elevated up to a power source voltage Vcc by the Tr Q5 made to be ON, and when the current Iin begins to decrease from the peak value, an output current of the Tr Q3 is held on the peak current value since the base potentials of Trs Q2, 3, 9 are held with the voltage of a capacitor C. With this arrangement, the peak value holding time of the signal current can be prolonged.</p>
申请公布号 JPH02290567(A) 申请公布日期 1990.11.30
申请号 JP19890111071 申请日期 1989.04.28
申请人 NEW JAPAN RADIO CO LTD 发明人 HIRAGA KIMIHISA
分类号 G01R19/04 主分类号 G01R19/04
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