SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: To enlarge the data transmission width between a cache and a main storage device by enabling an SRAM and DRAM cell arrays to be operated on the same bit line with an interface means. CONSTITUTION: The device is provided with an interface means 20 for electrically connecting or separating; at least one or more DRAM bit line DBL that contains plural pieces of a dynamic memory element having a memory capacitor means C for storing a binary state; either an SRAM bit line DBL or a DRAM bit line DBL containing at least one or more static memory element having a memory flip-flop means FF for storing a binary state; and an SRAM bit line SBL. Consequently, a data transmission bus width can be enlarged between a cache and the main storage device.