| 摘要 |
PURPOSE:To eliminate need to use a counter circuit and to simplify the constitution of a shift register circuit by holding a constant state while (n) clock signals are inputted continuously and inverting the output data of the flip-flop of an (n+1)th stage in synchronism with an (n+1)th clock signal. CONSTITUTION:This shift register circuit is provided with (n+1) flip-flops FF1 - FFn+1 and the flip-flop FF1 inputs a preset signal at its clear terminal R and a clear signal at its preset terminal S. The flip-flops FF2 - FFn+1 input preset signals at their preset terminals S and clear signals at their clear terminals R. Then the output of the Qn+1 terminal of the flip-flop FFn+1 is inputted to one input terminal of a NAND gate 10, whose output signal is inputted to the clock terminals Cp of the flip-flops FF1 - FFn+1. Consequently, any counter circuit need not be used and the constitution of the shift register circuit can be simplified. |
