| 摘要 |
PURPOSE:To obtain a stable frequency scarcely having a jitter component by switching the number of counting of a write clock from a frequency divider by a selector. CONSTITUTION:From a start point, a counter 105 counts a read-out clock (n) outputted from a frequency divider 109, its count value (f) is outputted, and when it coincides with an output (h) of a latch circuit 103 by a comparator 104, a coincidence detection output (g) is outputted. By the timing of a fall of the output (g), the counter 105 is reset, the circuit 103 latches an output value (e) of a selector 102 and outputs the output (h), and a flip-flop 110 inverts repeatedly an output (i). A phase comparator 106 inputs the output (i) and a head switching signal generator pulse (a) and outputs a phase comparison output (j). A low-pass filter 107 inputs the output (j) and brings it to band limit, and thereafter, a VCO 108 outputs a clock of a frequency which rises and falls by an output voltage of the filter 107, and outputs the clock (n) obtained by bringing the above clock to (mo) frequency division by the frequency divider 109. In such a way, a stable frequency scarcely having a jitter component can be obtained. |
