| 摘要 |
<p>PURPOSE: To make it possible to remove a semistable event caused by a clock signal and an asynchronous data signal by including a disabling circuit which invalidates the system clock signal for a specific time following the detection of transition of a data signal. CONSTITUTION: The data signal is received by the input 30 of an edge detector 32 and the input 34 of a clocked device 36 and the output 38 of the edge detector 32 is a control signal connected to the input 40 of a clock disabling/ reenabling circuit 42. The system clock signal is received by the input 44 of the circuit 42, whose output 46 is connected to the clock input 48 of the device 36. When data signal transition is caused, the edge detector 32 detects this transition and controls the clock disabling/reenabling circuit 42 to invalidate the system clock 56 for a setup time following the data transition. Consequently, any possibility of the semistable event is removed.</p> |
