| 摘要 |
PURPOSE: To improve resolution while keeping stability and low noise characteristics by forming a total digital phase error signal by synthesizing the output signals of a digital phase detection circuit and an analog phase detection circuit. CONSTITUTION: The digital phase detection circuit is provided with an up/down counter 6 to which a separate synchronous pulse signal VCS, phase clock reference pulse signal PL and clock pulse signal CPS are supplied, and a digital error signal DES is generated by a DFF 7. The analog phase detection circuit is provided with a capacitor charging/discharging circuit 8, exclusive OR gate 9, voltage comparator 11, control and timing logic circuit 12 and latch 13 and the separate synchronous pulse signal VCS is supplied to the latch 13. The charging voltage of a capacitor 16 proportional to an analog phase error is supplied to the control circuit 12 and a digital error signal AES is generated. The digital error signals DES and AES are added by a synthesizer circuit 20 and a total digital phase error signal DPE is formed. |
