Quadruple word, multiplexed, paged mode and cache memory.
摘要
<p>A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.</p>
申请公布号
EP0398191(A2)
申请公布日期
1990.11.22
申请号
EP19900108942
申请日期
1990.05.11
申请人
COMPAQ COMPUTER CORPORATION
发明人
THOMA, ROY E., III;MILLER, JOSEPH P.;SKELTON, BILL;TAYLOR, MARK;BONELLA, RANDY M.