Output buffer for reducing switching induced noise.

摘要

An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor (N1) element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown (R1) delay resistance element of selected value is coupled in series between the control terminal leads of the secondary (N1) and primary (N3) pulldown transistor elements. The secondary pulldown transistor (N1) element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor (N3) element control terminal lead. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown (N3) transistor element. The separate pulldown delay resistance (R1) element delays turn on of the primary pulldown transistor (N3) element a specified time delay after turn on of the secondary pulldown transistor (N1) element during transition from high to low potential at the output. As result ground bounce is divided into two spikes and the ground rise in potential is constrained to approximately one half that of conventional ground bounce levels. A secondary pullup transistor element with associated noise reduction components can similarly be used on the supply side to reduce Vcc droop.