| 摘要 |
<p>A data processing system contains a scalar unit (1), a vector unit (2), and a storage. The scalar unit (1) receives scalar instructions and vector instructions, carries out scalar data processing in accordance with the scalar instruction, and transfers the vector instruction to the vector unit (2), and the vector unit (2) receives the vector instruction from the scalar unit (1), carries out vector data processing in accordance with the vector instruction, and contains a post pending signal generating circuit (81-86, 201) for generating a post pending signal which is made active when a post instruction is received from the scalar unit (1) and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction. The scalar unit (1) further contains, a wait instruction detecting circuit for detecting a transfer of a wait instruction to the vector unit (2), and an interlock control circuit (111-114) for suspending executions of instructions which follow a wait instruction which is detected in the wait instruction detecting circuit and each including an operation to access the storage until the post pending signals changes from active to inactive.</p> |
