| 摘要 |
PURPOSE:To detect the coincidence of digital data by using abbreviated element configuration at high speed by constituting a multi-input logical gate of the bipolar transisor (TR) of multi-emitter configuration. CONSTITUTION:The multi-input logical gate G2 is constituted of the bipolar TR Q1 of the multi-emitter configuration. As for the TR Q1, by pulling up each emitter to a supply potential Vcc side respectively by n-channel MOS TRs Mn21 to Mn 28, and simultaneously, by pulling up their common base to the supply potential Vcc side through a resistor R1, the total logical sum of logic by each emitter is outputted from a collector side. Thus, the number of elements and the number of gate stages at the part of the multi-input logical gate is abbreviated, and the coincidence of the digital data of multi-bit length can be detected at high speed by using the abbreviated element configuration which is easy to form even in a semiconductor chip. |
