Method and arrangement for generating a correction signal for a digital clock recovery means

摘要

A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment.