发明名称 LOGICAL INTEGRATED CIRCUIT
摘要 PURPOSE:To simplify the check of troubles by checking the parity of each output signal from an AND array generating the AND of an output signal of a decoding circuit and an OR array generating an optional OR of the AND array. CONSTITUTION:An AND array 2 generates an optional AND of output signals of a decoding circuit 1 decoding external input signals. An OR array 3 generates optional OR of output signals of the AND array. A register circuit 4 controls the output signals of the AND array 2. Parity check circuits 51, 52, 53 check the parity of output signals of a decoding circuit 1, the AND array 2 and the OR array respectively. Troubles are checked by observing the output signals of the parity check circuits 51, 52, 53.
申请公布号 JPS57206961(A) 申请公布日期 1982.12.18
申请号 JP19810092505 申请日期 1981.06.16
申请人 NIPPON DENKI KK 发明人 YAMADA TERUHIKO
分类号 G06F7/00;G06F11/10;H03K19/177 主分类号 G06F7/00
代理机构 代理人
主权项
地址