| 摘要 |
An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T6) has its base connected to the collector of the first transistor (T3). A first resistor (R10), a second resistor (R11) and a third resistor (R12) are disposed in series between the emitter of the third transistor and a reference voltage (UREF) source. The point B common to the resistors R11 and R12 is coupled to the base of the second transistor (T4).
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