发明名称 CLOCK GENERATOR
摘要 <p>PURPOSE:To operate a system more surely by providing a clock generator with a ready signal generating circuit to give the function which outputs a multiword signal capable of coping with even a DRAM nibble mode. CONSTITUTION:A clock generator 2 incorporates a ready signal generating circuit 21 which generates a ready signal used for a microprocessor. The circuit 21 outputs plural signals for transfer data indicating that effective data is outputted to an external device at the time of read of the processor 3 and that the external device takes in data at the time of write. At this time, a wait control signal is outputted to the generator 2, and the circuit 21 generates a ready signal after inserting a required wait cycle. Thus, the circuit 21 has the function which outputs the multiword signal capable of coping with the DRAM nibble mode, and the system is operated more surely.</p>
申请公布号 JPH02281347(A) 申请公布日期 1990.11.19
申请号 JP19890104143 申请日期 1989.04.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 KANEKO KOICHI
分类号 G06F12/00;G06F1/06 主分类号 G06F12/00
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