发明名称 HIGH SPEED FRAME SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To use the protection network of an inexpensive circuit constitution by bringing DATA and CLOCK which are inputted to frequency division in a prescribed frequency division ratio and outputting them, respectively. CONSTITUTION:A clock (CLOCK) is brought to frequency division in a prescribed frequency division ratio in a frequency dividing circuit 15 and brought to all phase output, and by a pulse detecting circuit 20 and a selecting circuit 25, one of the outputs brought to all phase output is outputted as a frequency- divided output. Also, input data (DATA) synchronizing with the CLOCK is outputted as extended pulse width by a D-type flip-flop 10, based on the CLOCK which is brought to frequency division and all phase output. In such a manner, the protection network of an inexpensive circuit constitution for operating by a low frequency, comparing with the transmission rate of the DATA and the CLOCK which are inputted can be used, and the whole device can be obtained at the low cost.</p>
申请公布号 JPH02281837(A) 申请公布日期 1990.11.19
申请号 JP19890101745 申请日期 1989.04.24
申请人 ANRITSU CORP 发明人 MESHIDA ETSUJI;ORIGASA MASAHIRO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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