| 摘要 |
<p>A programmable logic device architecture having a matrix of smaller functional units (20-28), each of which being a programmable logic array, and a set of fixed conductive lines (31, 32) connected to the functional unit inputs (29) and outputs (30), the conductive lines (31, 32) forming programmable interconnection matrices (33). The input pins (34a, 34b) can be programmably connected to any input (29) of any functional unit (20-28), and the outputs (30) of functional units (20-28) can be programmably connected to any input (29) of any functional unit. Output pins (40a-40h) connect directly to outputs (30) of functional units (20-28). The interconnection matrices (38) may be a simple array of crossing conductive lines with crossings connected by EPROM, or EEPROM switches.</p> |
