发明名称 CHIP-ON-BOARD OPTIMUM INNER LEAD TIP DESIGNING SYSTEM
摘要 PURPOSE:To enable an optimum inner lead tip to be designed in a short time by calculating the designable range of an inner lead tip and then repeating averaging. CONSTITUTION:The chip boundary line of an inner lead tip and the designable range of the inner lead tip are calculated by using the pat coordinates and chip external shape, and bonding information previously and the assembly conditions excluding adjacent conditions input from the keyboard and designing conditions of the inner lead tip. Then, the tentative inner lead tip is placed in the middle of the designable range of the inner lead tip, the inner lead tip is moved within the designable range of each inner lead tip, the tip gap is averaged, the designing conditions of the inner lead tip are gradually changed so that the inner lead tip may meet the requirement of adjacent conditions, and averaging is repeated. Thus, it becomes possible to design an optimum inner lead tip in a short time.
申请公布号 JPH02278744(A) 申请公布日期 1990.11.15
申请号 JP19890100469 申请日期 1989.04.19
申请人 NEC CORP 发明人 TOMOTA HIROSHI
分类号 H01L21/60;G06F17/50 主分类号 H01L21/60
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