发明名称 FAULT TOLERANT MEMORY SYSTEM
摘要 PURPOSE: To improve the total reliability of a memory system by setting at least one output bit from a memory unit related to a correction impossible error to a fixed value at the time of generating the error so as to improve the reproductivity of a hard error. CONSTITUTION: Each of seventy two memory units 10 (chip #1 to #72) supplies a single bit for one system level register 25 and the system level register 25 outputs data through a system level error correction circuit(ECC) 30. When the correction impossible error related with the given chip then, the output of the chip is forcibly made a fixed value. As the result of this, it is certain that system level error display is displayed continually so that a system level error correction and detection circuit is capable of executing correction by complementing or recomplementing for the forced reproducing possibility of the chip error. Thereby the reproductibity of the hard error is improved to improve the total reliability of the memory system.
申请公布号 JPH02278449(A) 申请公布日期 1990.11.14
申请号 JP19900056827 申请日期 1990.03.09
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 ROBAATO MAACHIN BUREIKU;DAGURASU KUREIGU BOOSEN;CHINNRONGU CHIEN;JIYON ATOKINSON FUIFUIIRUDO;HAWAADO REO KARUTAA;TEINNCHIII RO
分类号 G06F12/16;G06F11/10 主分类号 G06F12/16
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